This application claims priority under 35 USC § 119 to Korean Patent Application No. 2006-116644 filed on Nov. 24, 2006 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to time-to-digital converters, and more particularly, to a time-to-digital converter with low and high resolution converters for high resolution and wide measurement range.
2. Background of the Invention
A time-to-digital converter (TDC) measures a time difference between signals. Traditionally, the time-to-digital converter has been used in a laser range finder. Recently, the time-to-digital converter is used in a digital phased locked loop.
FIG. 1 is a timing diagram illustrating fundamental operations of a time-to-digital converter. The time-to-digital converter compares two signals for generating a digital code corresponding to a time difference between the two signals. The time-to-digital converter measures the time difference between a first signal and a second signal in units of a quantization step tq. The measured time difference tm may be different from an actual time difference ta.
The difference between the measured value tm and the actual value ta corresponds to a quantization error. The quantization error may be as large as the quantization step tq. A high resolution time-to-digital converter has a relatively small quantization step tq, and a low resolution time-to-digital converter has a relatively large quantization step tq.
FIG. 2A shows a circuit diagram of a conventional time-to-digital converter 200 with a single delay line. The time-to-digital converter 200 includes a delay line 210 for transmitting a first signal, a reference line 220 for transmitting a second signal, and a comparator 230 that compares voltages at nodes of the delay line 210 with the voltage of the reference line 220. The comparator 230 includes flip-flops 231, 232, 233 and 234, each having a respective input coupled to a respective node of the delay line 210 and a respective clock terminal coupled to the reference line 220.
The time difference between the first signal and the second signal is determined according to outputs Q1, Q2, Q(n−1), and Qn of the flip-flops 231, 232, 233 and 234. Each of the delay units 211, 212 and 213 in the delay line 210 may be an inverter having a delay time of 50 ps such that a resolution of the time-to-digital converter in FIG. 2B is about 50 ps.
FIG. 2B is a plot of a time difference versus the output of the time-to-digital converter 200 of FIG. 2A. Referring to FIG. 2B, the time difference between the first and second signals is measured by units of a quantization step. When an error between the measured time difference and the actual time difference is smaller than the quantization step within a dead-zone, the time-to-digital converter 200 may determine that a phase of the first signal is same as a phase of the second signal.
Such a dead zone in FIG. 2B may cause jitter in an all-digital phase-locked loop (ADPLL) operating at a high frequency with the time-to-digital converter 200. The resolution of the time-to-digital converter should be increased to reduce the dead zone.
FIG. 3A is a circuit diagram of a conventional time-to-digital converter 300 including a vernier delay line. The time-to-digital converter 300 has two delay lines including a first delay line 310 and a second delay line 320 in contrast to the time-to-digital converter 200 of FIG. 2A. Each of a plurality of delay units 311, 312 and 313 of the first delay line 310 has a first delay time that is different from a second delay time of each of a plurality of delay units 321, 322 and 323 of the second delay line 320. For example, the first delay time for each of the delay units 311, 312 and 313 of the first delay line 310 is 50 ps, and the second delay time for each of the delay units 321, 322 and 323 of the second delay line 320 is 55 ps.
The time-to-digital converter 300 also includes a comparator 330 with a plurality of flip-flops 331, 332, 333 and 334. Each of the flip-flops 331, 332, 333 and 334 has a respective input coupled to a corresponding node between the delay units of the first delay line 310, and has a respective clock terminal coupled to a corresponding node between the delay units of the second delay line 320. The quantization step (i.e., resolution) of the time-to-digital converter 300 including the vernier delay line is 5 ps.
FIG. 3B is a plot of a time difference versus the output of the time-to-digital converter 300 of FIG. 3A. Referring to FIG. 3B, the time difference between the first and second signals is measured by units of the quantization step. The quantization step of the time-to-digital converter 300 of FIG. 3A is smaller than the quantization step of the time-to-digital converter 200 of FIG. 2A.
Thus, the time-to-digital converter 300 has a reduced dead zone. However, because of the smaller quantization step of the time-to-digital converter 300, a measurement range of the time difference of the first and second signals is reduced. Thus, the time-to-digital converter 300 may not measure a time difference larger than a measurement range.
In addition, an increase in the number of delay units and flip-flops for expanding the measurement range disadvantageously increases chip size. Furthermore, a time-to-digital converter including a vernier delay line occupies larger chip size than a time-to-digital converter including a single delay line, if both of the time-to-digital converters include the same number of flip-flops.